Neuromorphic energy-efficient secure accelerators
Neuromorphic energy-efficient secure accelerators based on phase change materials augmented silicon photonics.
Role of Argotech in Neuropuls: Semiconductor packaging specialist
Main task for Argotech: Development of packaging solutions for FPGA driving.
The architecture of the photonic chip will be analysed to allow the FPGA driving circuit to be optimally connected to the photonic chip for a successful demonstration. A suitable packaging strategy will be adopted to maximise the performance and impact of the final demonstrator circuit.
Secondary task for Argotech: Development of common logic for photonic architectures accelerator interface with EU partners.
Project result for Argotech: Fully customized platform for hosting FPGA driving circuit connected to photonic chip.
The Future of Computing: Unlocking the Potential of Neuromorphic Technology for Low-Power and Secure Edge Computing. With the rise of self-driving vehicles, IoT, and Industry 4.0, the need for processing massive amounts of data locally and securely has never been greater. Traditional electronic computing systems have limitations such as high latency and low energy efficiency, which are no longer suitable for these applications. Neuromorphic computing, a brain-inspired approach, is the solution to these problems.
However, current neuromorphic electrical computing systems have their own limitations, which is why the NEUROPULS project is developing next-generation low-power and secure edge-computing systems. By utilizing novel photonic computing architectures and security layers based on photonic PUFs, augmented silicon photonics CMOS-compatible platforms, and emerging non-volatile phase change materials, this project aims to demonstrate a two order of magnitude improvement in energy efficiency. With RISC-V compliant interfaces and a novel full-system simulation platform, NEUROPULS will revolutionize the future of computing.
NEUROPULS will develop -for the first time- secure hardware accelerators based on novel neuromorphic architectures and PUF-based security layers leveraging the benefits offered by the integration of photonics, PCMs and III-V materials. This integration will provide superior security, energy-efficiency, and speeds for spiking and formal recurrent NNs when compared to current available technology for the selected use-cases.
- Objective 1: Development of a CMOS-compatible platform addressing the integration of silicon photonics with PCMs and III-V materials
- Objective 2: Development of a low-power and secure RISC-V interfaced neuromorphic accelerator based on the integration of silicon photonics, novel PCMs, and Q-switched III-V lasers
- Objective 3: Development of a system-level simulation platform for PCM-based photonic low-power accelerators using photonic security layers
ALBORA TECHNOLOGIES SL
BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
ECOLE CENTRALE DE LYON – 3rd partner
ETHNIKO KAI KAPODISTRIAKO PANEPISTIMIO ATHINON
HEWLETT PACKARD ENTERPRISE BELGIUM
INESC ID – INSTITUTO DE ENGENHARIADE SISTEMAS E COMPUTADORES, INVESTIGACAO E DESENVOLVIMENTO EM LISBOA
POLITECNICO DI TORINO
TECHNISCHE UNIVERSITAT BERLIN
UNIVERSITA DEGLI STUDI DI VERONA
UNIVERSITE DIJON BOURGOGNE – 3rd partner
This project has received funding from the European Union’s Horizon Europe research and innovation programme.
Grant agreement no. 101070238.